The present invention relates to controllers for producing a dual port function with a standard single port memory device.
Applications for dual port memories are widespread in asynchronously running multi-processor systems. Dual port memories relieve the system engineers of the task of reinventing the arbitration network and multiplexing network that must be placed around standard memory devices to simulate a dual port function. Generally, there are two approaches to the design of monolithic dual port memories. One is made from special memory cells that may incorporate separate read/write controls from both ports. Another design is to have an ordinary memory core with multiplexers and arbitration controllers placed around it directing proper dual port operations between the ports.
The first method, a special dual port cell design, shows better performance and has simpler peripheral control than the simulated dual port memory. FIG. 1 shows such a dual-access RAM cell. However, each dual port cell will occupy twice as much silicon as a normal cell. Therefore, for the monolithic integrated circuit design, this approach will be very costly and almost impractical for high density integration.
In the conventional application of the second approach the speed performance of the memory is limited. Each dual-port memory operation cycle has to be split into two internal cycles, enabling one master-contention circuit to handle all the arbitration that controls the multiplexing between ports. Also, because of the asynchronous nature of the dual-port address access, external READ/WRITE request clock signals are required to set up a queuing function. This resolves all the conflicting access requests.
A simulated dual port memory design is shown in FIG. 2. A random access memory (RAM) core 12 with a single port for address and data is shown. An arbitration network 14, upon receipt of a chip enable signal on line 16, couples the right addresses to RAM core 12 through an input switch 18. At the same time, the outputs are coupled to a right data input/output (I/O) line through a switch 20. After a complete read or write cycle, switches 18 and 20 can be reversed to couple to a left address input and a left data I/O.
A memory operation cycle that involves both ports is actually split into two internal cycles. One master contention circuit handles all arbitration and controls the multiplexing between ports. However, in order to set up a queuing function to resolve all the conflicting access requests and to fulfill all the asynchronous access requests from both sides, extra read/write request clocks are required, thus complicating the system. Furthermore, two internal cycles are needed to accomplish a system cycle and thus the speed performance is strictly limited.
An article on one dual port memory is in the 1985 IEEE Solid-State Circuits Conference, entitled "A 2K.times.9 Dual Port Memory" by Frank Barber, et al., of AT&T. A clocked static RAM is described which needs an external enable signal to initiate an access for either port.